This invention relates to a semiconductor device in which a comparatively thick insulating film is buried or formed in a field region and also a method of manufacturing such a semiconductor device.
In a semiconductor device using silicon as the semiconductor, more particularly a MOS semiconductor device, a thick insulating film is formed in a so-called field region between adjacent elements in order to eliminate defective insulation due to parasitic channels and also reduce the parasitic capacitance.
The inter-element isolation in such a semiconductor device, is attained by a well-known selective oxidation method. In this method, the element formation region is covered with an oxidizable mask, typically a silicon nitride film, and a thick oxide film is selectively formed over the field region through high temperature oxidation. According to this selective oxidation method, however, the field oxide film protrudes in the form of a bird's beak from the end of the silicon nitride film during the high temperature oxidation. This causes dimensional errors of the element formation region and also prevents high density integration of integrated circuits.
In another aspect, in the prior art selective oxidation method, a surface step of about one half of the field oxide film (which is about 0.7 to 1.0 .mu.m) in height is formed in the field region and element formation region after the formation of the field oxide film. This step remains as such in the subsequent steps to reduce the precision of the subsequent lithography. Also, the reliability of the metal lead is reduced at the step.
A BOX (buried oxide) method is also well known as a method which can eliminate the bird's beak and permits a flat buried field oxide film to be obtained.
The BOX method will now be briefly described with reference to FIG. 1. As shown in FIG. 1(A), a silicon substrate 1 is prepared, and it is selectively etched to a desired depth corresponding to the field film thickness with the element formation region covered with a mask 2 by the ordinary photoetching process. Then, as shown in FIG. 1(B) an impurity of the same conductivity type as the silicon substrate for the prevention of field inversion, for instance boron 3 in case of a P-type substrate, is injected by ion implantation into the field region by using the same mask 2. Subsequently, as shown in FIG. 1(C) a silicon oxide film 4 to be buried in the field region is formed by using a lift-off process. The lift-off process may be carried out as follows. In the first place, a plasma CVD SiO.sub.2 film is deposited over the entire surface of the wafer shown in FIG. 1(B). Then, etching for about one minute is done using, for instance, ammonium fluoride. As a result, a portion of the plasma CVD SiO.sub.2 film deposited on the side surfaces of the raised portion formed at the boundary between the field region and element formation region is selectively removed because the etching speed for this portion is higher than that for the rest of the plasma CVD SiO.sub.2 film formed on the non-raised or flat portion of the wafer by 3 to 20 times. The mask remaining on the element formation region is subsequently removed, whereby the portion of the plasma CVD SiO.sub.2 film remaining on the mask is also removed. In this way, the plasma CVD SiO.sub.2 film is left only in the field region. A narrow groove 5 having a V-shaped sectional profile is formed at the boundary between the field region and element formation region as shown in FIG. 1(C).
Afterwards, as shown in FIG. 1(D) a CVD SiO.sub.2 film 6 is deposited to fill the narrow groove 5. At this time, a groove 7 is formed in the CVD SiO.sub.2 film in a portion thereof over the narrow groove 5 mentioned above. Thereafter, a film 8 which has fluidity and can be etched at the same rate as the CVD SiO.sub.2 film is formed to fill the groove 7 thereby providing a flat surface.
Subsequently, the fluid film 8 and CVD SiO.sub.2 film 6 are etched away, and further etching is carried out to expose the silicon in the element formation region. As a result, a substantially flat field region 9 consisting of the CVD SiO.sub.2 film and plasma CVD SiO.sub.2 film is formed, as shown in FIG. 1(E). A desired element is then formed in the element formation region 10 by the ordinary method.
In the above BOX method, the dimensions of the element region are defined solely by the dimensions of the mask formed for the photoetching process if reactive ion etching (RIE) which is free from side etching is used for the etching of the silicon substrate. Thus, it is possible to reduce the dimensional error of the element formation region to zero. In addition, a structure having a perfectly flat surface can be obtained, so that it is possible to increase the precision in the subsequent lithography and extremely improve the reliability of leads.
Problems, however arises with the prior art BOX method in case when forming a diffusion layer 11 (for instance of N.sup.+ -type) in the element region 10, then forming an insulating film 12 and an opening or hole 13 in the film by using ordinary lithography and electrically connecting a metal lead 14 and the diffusion layer 11 by making use of the hole 13, as shown in FIG. 2.
To form the hole 13 over the diffusion layer 11 as in FIG. 2, it is necessary to provide a mask register margin in the lithographic techniques. Recent trend for forming finer semiconductor elements, however, demands a very small width of the hole 13. In practice, however, it is technically difficult to form hole 13 having such a small width.
To alleviate the problems in the lithography of forming holes as discussed above, it may be thought to form the hole 13 such that it partly overlap the diffusion layer 11 and field region 9 as shown in FIG. 3A. By so doing, the semiconductor device integration density may be promoted.
However, where the hole 13 is formed to partly overlap the field region 9, part 14 of the field oxide film 9 is also etched away at the time of the hole formation as shown in FIG. 3(B). Therefore, abnormal electric connection of a subsequently formed metal lead and the silicon substrate is liable to result.
Serious restriction, therefore, is imposed on the integration density of the semiconductor device due to limitations on the size of holes for obtaining electric connection of metal leads although the dimensions of elements may be reduced by the BOX method.